Provide one-stop full solution with a platform for academic staff of the university and industry people for conducting research and development addressing the VLSI design issues including custom chip, VLSI design problem, and solution provider for VLSI circuits in embedded system, customised system, semi ready-system and fully ready-system applications in industry, computing, mixed signal and wireless applications.
Since the invention of transistor in 1947 and the invention of miniaturised transistor circuit in 1958 and eventually building of first planar miniaturized transistor in 1960, integrated circuit technology has evolved from small scale integration SSI into today's VLSI/ULSI scaling. The integrated circuit technology has played a tremendous role in the advancement of ICT particularly in the computer application, control, communication, space exploration, etc. Today's total world sale of semiconductor is more than USD 330 billion a year. More than half of the sale comes from digital VLSI integrated circuit related products. Being an institution of higher learning with the aims of not only teaching but also much emphasising on research and development, the push to be forefront and authority in the selected research area is a need. Thus, choosing research and development in the area of VLSI design, which has not seen the end of the boundary of research and development, would comply and accelerate for achieving the aims of the university in the near future.
The centre would provide training, consultation, design provider, and research & development for VLSI integrated circuit design in terms of design methodology, algorithmic flow. The activity also includes packaging design and test/measurement methods and implementation for students, academic staff, researchers, and industrialists.
|Tang Chong Ming|
|Khaw Mei Kum|
|Lim Soo King|
|Ooi Chek Yee|
|Tan Kia Hock|
|Yang Chuan Choong|
|Yap Vooi Voon|
Two system architectures were studied:
- traditional bus interconnect 4 cores
- network-on-chip interconnect 4 cores
The NoC based architecture is extended to many (>4) cores. Verification suits were extended and developed from the 4 cores system to verify the design and study the performance. The result is a scalable verification environment that can be used to study systems with any number of cores and various on-chip network interconnects.
A new and UTAR-owned on-chip network router.
Adaptive routing algorithm for different class of application traffics
- RTL design
- UVM based verification suits
- Performance benchmarking
System Using NoC Communication for Parallel Coarse-grained Data Processing,
Dicky Hartono et al, International Conference ConMedia 2013 UMN-IEEE, Nov 2013,
IEEE Conference Proceeding (ISBN 978-602-8944-21-2 (PDF Files), ISBN
A Scalable Bootloader and Debugger Design for An NoC-based Multi-processor SoC, Dicky Hartono et al, International Conference ConMedia 2015 UMN-IEEE, Nov 2015, Jakarta.
A scalable and configurable Multiprocessor System-on-Chip (MPSoC) virtual platform for hardware and software co-design and co-verification, Arya Wicaksana et al, International Conference ConMedia 2015 UMN-IEEE, Nov 2015, Jakarta.
Exploring Software-Defined Radio on Multi-Processor System-on-Chip, Dareen K. Halim et al, International Conference ConMedia 2015 UMN-IEEE, Nov 2015, Jakarta.
A Reconfigurable and Scalable Verification ENvironment for NoC Design, Zhen Ning Lim et al, International Conference ConMedia 2013 UMN-IEEE, Nov 2013, IEEE Conference Proceeding (ISBN 978-602-8944-21-2(PDF Files), ISBN 978-602-8944-22-9(CD Proceeding)).
Felix Lokananta, S.W. Lee, M.S. Ng, Tao Lin, C.M.Tang. (2013, Nov.). An Advanced Ultra Low Power, Multi-voltage, Multi-corner, Multi-mode, SoC Physical Design Implementation. New Media Studies (CoNMedia), 2013 Conference.
Felix Lokananta, S.W. Lee, M.S. Ng, Z.N. Lim, C.M.Tang. (2015, Nov.). UTAR NoC: Adaptive Network on Chip Architecture Platform. New Media Studies (CoNMedia), 2015 Conference.