RUMPS401 MPSoC for IoT System and Education

UTAR VLSI Projects

-        A System Using NoC Communication for Parallel Coarse-grained Data Processing

-        A reconfigurable and scalable verification environment for noc design

-        A scalable and reconfigurable verification and benchmark environment for Network on Chip architecture

-        Lotus-G: The PVT Multicore TLM Virtual Platform for Early RUMPS401 Software Development

-        Exploring software-defined radio on Multi-Processor System-on-Chip

Rahman University Multi-Processor System (RUMPS401) 

Designed by the Centre for VLSI Design, Universiti Tunku Abdul Rahman (UTAR) with the collaboration of GLX Technologies and Silterra Malaysia Sdn Bhd. This is the first Multi-Processor System-on-a-Chip (MPSoC) produced in Malaysia  utilising 4 ARM Cortex-M0 cores with UTAR proprietary network-on-chip router and power management scheme.

Rahman RUMPS401 Features Summary

  • 4 ARM Cortex-M0 processor cores each with 8 KB SRAM and 32KB SST SuperFLASH ROM
  • On-chip inter-processor communication network (NoC) using UTAR’s own AHB-to-NoC bridge and Adaptive NoC Router IPs
  • The ARM M0 Education Design Start Kit (provided via the ARM University Programme) was modified to be usable in SoC silicon by adding a boot-loader, debugger and power management
  • Hardware AES for Encryption, MAC for DSP functions
  • Power Management unit, deep sleep mode 12-14 uA
  • Memory management and control units (SRAM & FLASH), SPI, UART, Parallel Ports, GPIO,
  • DFT features: FLASH Test Wrapper, SRAM BIST, Scan and Oscillator test
  • SilTerra 0.18um CMOS Embedded FLASH Process (C18E+LP)
  • Step & Repeat size 5240um X 5240um, equivalent 1.22 Million Gates
  • 100-pin QFP package


System-on-chip design house. Foundry. Design tools.
IP cores from university programme provider.